Welcome to NANO-TEC

NANO-TEC seeks to build a community of academic researchers in nanoelectronics, addressing specifically research in Beyond CMOS from the combined technology and design perspectives. A methodology for continued consultation and analysis of research needs and trends will be developed. The main activity will be a workshop series with invited experts, preceded by a methodology-contents preparation phase and subsequent analysis and documentation, both by the consortium. Apart of determining what is relevant for Beyond CMOS devices and design, benchmarking and SWOT analyses will be performed.

Now available: Recommendations on Beyond CMOS Nanoelectronics Research

Recommendations on Beyond CMOS nanoelectronics researchThe NANO-TEC project consortia has finalized its "Recommendations on Beyond CMOS Nanoelectronics Research" based on presentations and discussions during the workshop series held between January 2011 and November 2012. It is anchored in the grand technological challenges in information processing, communications, based on memory and logic devices, circuits and architectures with a view to the time when CMOS scaling begins to loose some of its advantages over emerging nanoelectronic technologies.

This report is available here as a PDF.

NANO-TEC Yellow Pages on European Competences in future Nanoelectronics available

NANO-TEC Yellow PagesThe NANO-TEC project announces its ‘Yellow Pages‘ (YP) to be publicly available. The Yellow Pages comprise an information repository which offers search for and access to experts, institutions, projects, working groups and results in the field of future nanoelectronics, as in Beyond CMOS, in Europe.

Draft of NANO-TEC-Recommendations on beforehand of Workshop 4 available!

Dear Workshop participant,

the NANO-TEC project consortia has extracted the results from the three previous workshops in Granada (January 2011, Athens (October 2011) and Lausanne (May 2012) and gathered them in a draft report including some recommendations.

This draft report is available here for registered users.

Registration for the final NANOTEC workshop on November, 6-7, 2012 in Barcelona, Spain is open

Barcelona, Parque GuellThe program of the final NANOTEC workshop taking place
on November, 6-7, 2012 in Barcelona, Spain
is online and the registration is open.

Slides of the NANOTEC-Tutorial at ESSCIRC/ESSDERC available now

The NANO-TEC project has held a half day tutorial at the ESSDERC/ESSCIRC Conference in Bordeaux on Monday, September 17, 2012. This Tutorial has been on the ECOSYSTEMS TECHNOLOGY and DESIGN for NANOELECTRONICS in Europe and has presented the current outcome of the EU project NANOTEC.Bordeaux

MemCo workshop "Memristors for Computing" on 11/19-21/2012

The MemCo workshop "Memristors for Computing" will be held on the 19-21 November 2012 at the Villa Clythia, Fréjus, France. It aims to bring together different communities interested in memristor devices and their applications, from condensed matter to hardware implementation. The deadline to register and submit an abstract is July 31st, 2012.

Download: 

NANO-TEC poll on European capabilities regarding Technology-Design of beyond CMOS technologies

The NANO-TEC project is working on a description of the current status of the European capabilities regarding Technology-Design of the technologies benchmarked during the NANO-TEC workshop 2. The project urgently needs your experience and opinion on that to be filled in in the questionaire to be found at www.fp7-nanotec.eu/workshop3/poll. So please contribute!

Workshop 3: SWOT Analysis of the Technology-Design Ecosystem, May 30-31

The report on the 3rd NANO-TEC workshop, written as deliverable for the EC, is now available here.


For the presentations during this workshop follow the menue on the left or see here.


The 3rd NANOTEC workshop took place on May, 30-31, 2012 in Lausanne, Switzerland. The program included a series of plenary presentations on several selected technologies, followed by a panel discussion on the programmatic and explorative perspectives of these technologies in which the results of the SWOT analysis will be assesed.

Location: BEAU RIVAGE PALACE HOTEL,
                Place du Port 17-19
                CH 1000 LAUSANNE 6 - Switzerland
                Tel. : +41 (0)21 613 33 33

NANO-TEC at the Design Automation & Test (DATE) Conference 2012

Plenum DATE 2012

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