The document contains the recommendations arrived at during the discussion and consultation process organised by the project NANO-TEC. It is anchored in the grand technological challenges in information processing, communications, based on memory and logic devices, circuits and architectures with a view to the time when CMOS scaling begins to loose some of its advantages over emerging nanoelectronic technologies. The document was compiled by the EU FP7 ICT project NANO-TEC, based on presentations and discussions during the workshop series held between January 2011 and November 2012.
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"Recommendations for the Technology-Design Ecosystem for Nanoelectronics"
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