Janczyk, Grzegorz

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Title: 
Dr.
First Name: 
Grzegorz
Last Name: 
Janczyk
Kind of Address: 
Headquarter Address
Address: 
Al. Lotnikow 32/46
Zipcode: 
02-668
City: 
Warsaw
Country: 
Poland
Company / Institute: 
Bio and Interests: 
Grzegorz Janczyk received the M.Sc degree (with honors) and P.hD degree in electronic engineering from the Warsaw University of Technology, Poland in 1999 and 2005 respectively. Since then, he has been with the Institute of Microelectronics and Optoelectronics, VLSI Engineering and Design Automation _ Division – (IMiO-WUT), at the same university. In 2006 he joined the Institute of Electron Technology (ITE). He is an Assistant Professor in IMiO-WUT and ITE. From 2012 he is head of the Department of Integrated Circuits and Systems in the Institute of Electron Technology. His main Ph.D. related interests cover device modeling along with technological SOI fabrication process modeling and development of SOI-MOS transistor models. Multi-domain device modeling using Verilog language also belongs to the range of his professional interests. Statistical yield simulations and mismatch modeling are secondary field of interest. He is also C++ programmer.